1. Field of the Invention
The invention relates in general to a buffer in a memory access system. More particularly, the invention relates to a buffer in a motherboard used for enhancing data access speed of memories.
2. Description of the Related Art
In recent years, dynamic random access memory (DRAM) has evolved from the earliest non-synchronous dynamic random access memory (DRAM) to enhance data out (EDO) dynamic random access memory, and further to the currently widely applied synchronous dynamic random access memory (SDRAM). Each transmutation provides a great enhancement in access speed of the memory system. Most of the high-speed buses employ a source synchronous design such as the AGP Bus, the double data rate dynamic random access memory (DDR DRAM), and the RAMBUS. In addition, as a high data transmission speed requires a set of complementary data strobe signals, combination of the source synchronous design and provision of a set of complementary data strobe signals have become a leading trend in memory system design.
The market for dynamic random access memory system is still enormous. Generally speaking, a macro-revolution of this product takes three to five years. Thus, the speed of performance enhancement for a memory system relative to the growth of data transmission between microprocessor and storage device or microprocessor and graphic apparatus is slow. Especially in the use of the Internet, where a significant amount of data transmission is required, the inferior memory bandwidth seriously degrades the sensory enjoyment of the users.
FIG. 1 is a block diagram showing a conventional memory system on a mother board. The control chip set 100 is directly coupled to a memory module 140. The control chip set 100 and the memory module 140 use the same system clock as the reference for data transmission speed. Being limited by the current dynamic random access memory, the control chip set 100 has to lower the speed of the read/write instruction and data transmission to complete the data read/write operation with a transmission speed allowed by the memory system.
The invention provides an apparatus for varying data access speed, so that the current standard dynamic random access memory system can have a multiple data transmission rate. In one embodiment of the invention, a buffer is provided. The buffer is coupled between a control chip set and several memory modules to disassemble the write data sent from the control chip set to the memory modules and to assemble the read data sent from the memory modules to the control chip set.
The invention provides an apparatus for varying data access speed. A single memory read/write interface sent from a memory is converted into a high speed complementary signal of source synchronous design.
The above apparatus can also isolate the electric connection between the control chip set and the memory module. The modulization of the system design is thus more flexible. For example, the consideration of sequence in layout design is easier.
The above apparatus can also reduce the pin counts with the bandwidth that maintains or increases data transmission speed. Therefore, the fabrication cost can be reduced, or the input/output (I/O) pins can be reserved for other applications.
In one embodiment of the invention, a buffer varying data access speed is provided. The buffer includes a phase lock loop circuit, a control chip set data I/O interface, a memory data I/O interface, a first-in-first-out (FIFO) memory from the control chip set to the memory, a FIFO memory from the memory to the control chip set, and a control signal generator. The phase lock loop circuit is responsible for generating various clock signals required for the buffer. The buffer is coupled to the control chip set and the memory modules. The write data from the control chip set is received by the FIFO memory from the control chip set to the memory. Thereby, the write data is disassembled and transmitted to the memory modules by the memory data I/O interface. The FIFO memory from the memory to the control chip set is responsible for receiving the read data from the memory modules. Once assembled by control chip set data I/O interface, the read data is then transmitted to the control chip set. The control signal generator generates proper read/write control and I/O control, so that the data transmission speed at the control chip set can be a multiple of the data transmission speed at the memory as expected. Alternatively, the phase lock loop circuit can be omitted by supplying the clock signals directly from the system.
With the above buffer, a respective memory module can be assembled to enhance the performance of the memory system to match data transmission speed of the microprocessor or other I/O interface.
Both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the invention, as claimed.